M1AFS600-PQ208 Datasheet, PDF (276/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

DC and Power Characteristics
RAM Dynamic Contribution—P_MEMORY
Operating Mode
P_MEMORY = (N_BLOCKS * PAC11 * ₂ * F_READ-CLOCK) + (N_BLOCKS * PAC12 * ₃ * F_WRITE-CLOCK)
N_BLOCKS is the number of RAM blocks used in the design.
F_READ-CLOCK is the memory read clock frequency.
₂ is the RAM enable rate for read operations—guidelines are provided in Table 3-17 on
page 3-27.
₃ the RAM enable rate for write operations—guidelines are provided in Table 3-17 on page 3-27.
F_WRITE-CLOCK is the memory write clock frequency.
Standby Mode and Sleep Mode
P_MEMORY = 0 W
PLL/CCC Dynamic Contribution—P_PLL
Operating Mode
P_PLL = PAC13 * F_CLKOUT
F_CLKIN is the input clock frequency.
F_CLKOUT is the output clock frequency.¹
Standby Mode and Sleep Mode
P_PLL = 0 W
Nonvolatile Memory Dynamic Contribution—P_NVM
Operating Mode
The NVM dynamic power consumption is a piecewise linear function of frequency.
P_NVM = N_NVM-BLOCKS * ₄ * PAC15 * F_READ-NVM when F_READ-NVM 33 MHz,
P_NVM = N_NVM-BLOCKS * ₄ *(PAC16 + PAC17 * F_READ-NVM when F_READ-NVM > 33 MHz
N_NVM-BLOCKS is the number of NVM blocks used in the design (2 inAFS600).
₄ is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state).
F_READ-NVM is the NVM read clock frequency.
Standby Mode and Sleep Mode
P_NVM = 0 W
Crystal Oscillator Dynamic Contribution—P_XTL-OSC
Operating Mode
P_XTL-OSC = PAC18
Standby Mode
P_XTL-OSC = PAC18
Sleep Mode
P_XTL-OSC = 0 W
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the
contribution.
formula
output
clock
by
adding
its
corresponding
contribution
(P_AC14
*
F_CLKOUT
product)
to
the
total
PLL
3-26
Revision 4