M1AFS600-PQ208 Datasheet, PDF (321/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Revision
v2.0, Revision 1
(July 2009)
Changes
The MicroBlade and Fusion datasheets have been combined. Pigeon Point
information is new.
CoreMP7 support was removed since it is no longer offered.
–F was removed from the datasheet since it is no longer offered.
The operating temperature was changed from ambient to junction to better reflect
actual conditions of operations.
Commercial: 0°C to 85°C
Industrial: –40°C to 100°C
The version number category was changed from Preliminary to Production, which
means the datasheet contains information based on final characterization. The
version number changed from Preliminary v1.7 to v2.0.
The "Integrated Analog Blocks and Analog I/Os" section was updated to include a
reference to the "Analog System Characteristics" section in the Device Architecture
chapter of the datasheet, which includes Table 2-46 • Analog Channel Specifications
and specific voltage data.
The phrase "Commercial-Case Conditions" in timing table titles was changed to
"Commercial Temperature Range Conditions."
The "Crystal Oscillator" section was updated significantly. Please review carefully.
The "Real-Time Counter (part of AB macro)" section was updated significantly.
Please review carefully.
There was a typo in Table 2-19 • Flash Memory Block Pin Names for the
ERASEPAGE description; it was the same as DISCARDPAGE. As as a result, the
ERASEPAGE description was updated.
The t_FMAXCLKNVM parameter was updated in Table 2-25 • Flash Memory Block
Timing.
Table 2-31 • RAM4K9 and Table 2-32 • RAM512X18 were updated.
In Table 2-36 • Analog Block Pin Description, the Function description for PWRDWN
was changed from "Comparator power-down if 1"
to
"ADC comparator power-down if 1. When asserted, the ADC will stop functioning,
and the digital portion of the analog block will continue operating. This may result in
invalid status flags from the analog block. Therefore, Microsemi does not
recommend asserting the PWRDWN pin."
Figure 2-75 • Gate Driver Example was updated.
The "ADC Operation" section was updated. Please review carefully.
Figure 2-92 • Intra-Conversion Timing Diagram and Figure 2-93 • Injected
Conversion Timing Diagram are new.
The "Typical Performance Characteristics" section is new.
Table 2-49 • Analog Channel Specifications was significantly updated.
Table 2-50 • ADC Characteristics in Direct Input Mode was significantly updated.
In Table 2-52 • Calibrated Analog Channel Accuracy 1,2,3, note 2 was updated.
In Table 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages,
note 1 was updated.
In Table 2-54 • ACM Address Decode Table for Analog Quad, bit 89 was removed.
Page
N/A
1-4
N/A
2-21
2-35
2-42
2-54
2-69
2-81
2-94
2-107
2-116
2-118
2-120
2-123
2-126
2-127
2-129
Revision 4
5-5