M1AFS600-PQ208 Datasheet, PDF (41/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Global Buffers with No Programmable Delays
The CLKBUF and CLKBUF_LVPECL/LVDS macros are composite macros that include an I/O macro
driving a global buffer, hardwired together (Figure 2-20).
The CLKINT macro provides a global buffer function driven by the FPGA core.
The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are pass-through clock sources and do not
use the PLL or provide any programmable delay functionality.
Many specific CLKBUF macros support the wide variety of single-ended and differential I/O standards
supported by Fusion devices. The available CLKBUF macros are described in the IGLOO, ProASIC3,
SmartFusion and Fusion Macro Library Guide.
Clock Source
CLKBUF_LVDS/LVPECL Macro CLKBUF Macro
PADN
PADP
Y
PAD
Y
CLKINT Macro
A
Y
Figure 2-20 • Global Buffers with No Programmable Delay
Clock Conditioning
None
Output
GLA
or
GLB
or
GLC
Revision 4
2- 25