M1AFS600-PQ208 Datasheet, PDF(275/334 Page) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

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M1AFS600-PQ208 Datasheet, PDF (275/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

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Fusion Family of Mixed Signal FPGAs

PS-CELL = NS-CELL * (PAC5 + (ï¡1 / 2) * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 3-16 on page 3-27.

FCLK is the global clock signal frequency.

Standby Mode and Sleep Mode

PS-CELL = 0 W

Combinatorial Cells Dynamic ContributionâPC-CELL

Operating Mode

PC-CELL = NC-CELL* (ï¡1 / 2) * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 3-16 on page 3-27.

FCLK is the global clock signal frequency.

Standby Mode and Sleep Mode

PC-CELL = 0 W

Routing Net Dynamic ContributionâPNET

Operating Mode

PNET = (NS-CELL + NC-CELL) * (ï¡1 / 2) * PAC8 * FCLK

NS-CELL is the number VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 3-16 on page 3-27.

FCLK is the global clock signal frequency.

Standby Mode and Sleep Mode

PNET = 0 W

I/O Input Buffer Dynamic ContributionâPINPUTS

Operating Mode

PINPUTS = NINPUTS * (ï¡2 / 2) * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

ï¡2 is the I/O buffer toggle rateâguidelines are provided in Table 3-16 on page 3-27.

FCLK is the global clock signal frequency.

Standby Mode and Sleep Mode

PINPUTS = 0 W

I/O Output Buffer Dynamic ContributionâPOUTPUTS

Operating Mode

POUTPUTS = NOUTPUTS * (ï¡2 / 2) * ï¢1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

ï¡2 is the I/O buffer toggle rateâguidelines are provided in Table 3-16 on page 3-27.

ï¢1 is the I/O buffer enable rateâguidelines are provided in Table 3-17 on page 3-27.

FCLK is the global clock signal frequency.

Standby Mode and Sleep Mode

POUTPUTS = 0 W

Revision 4

3- 25

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