M1AFS600-PQ208 Datasheet, PDF (245/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
ATRTNx
Temperature Monitor Return
AT returns are the returns for the temperature sensors. The cathode terminal of the external diodes
should be connected to these pins. There is one analog return pin for every two Analog Quads. The x in
the ATRTNx designator indicates the quad pairing (x = 0 for AQ1 and AQ2, x = 1 for AQ2 and AQ3, ...,
x = 4 for AQ8 and AQ9). The signals that drive these pins are called out as ATRETURNxy in the software
(where x and y refer to the quads that share the return signal). ATRTN is internally connected to ground.
It can be left floating when it is unused. The maximum capacitance allowed across the AT pins is 500 pF.
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have identical
capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed
descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on page 2-23.
Refer to the "User I/O Naming Convention" section on page 2-161 for a description of naming of global
pins.
JTAG Pins
Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,
even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the Fusion
part must be supplied to allow JTAG signals to transition the Fusion device.
Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and
simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used,
the VJTAG pin together with the TRST pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND or VJTAG through
a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired
state.
Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Refer to
Table 2-183 for more information.
Table 2-183 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance^{2, 3}
VJTAG at 3.3 V
200  to 1 k
VJTAG at 2.5 V
200  to 1 k
VJTAG at 1.8 V
VJTAG at 1.5 V
500  to 1 k
500  to 1 k
Notes:
1. Equivalent parallel resistance if more than one device is on JTAG chain.
2. The TCK pin can be pulled up/down.
3. The TRST pin can only be pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
Revision 4
2- 229