M1AFS600-PQ208 Datasheet, PDF (24/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Array Coordinates
During many place-and-route operations in the Microsemi Designer software tool, it is possible to set
constraints that require array coordinates. Table 2-3 is provided as a reference. The array coordinates
are measured from the lower left (0, 0). They can be used in region constraints for specific logic
groups/blocks, designated by a wildcard, and can contain core cells, memories, and I/Os.
Table 2-3 provides array coordinates of core cells and memory blocks.
I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed
because there is not a one-to-one correspondence between I/O cells and edge core cells. In addition, the
I/O coordinate system changes depending on the die/package combination. It is not listed in Table 2-3.
The Designer ChipPlanner tool provides array coordinates of all I/O locations. I/O and cell coordinates
are used for placement constraints. However, I/O placement is easier by package pin assignment.
Figure 2-7 illustrates the array coordinates of an AFS600 device. For more information on how to use
array coordinates for region/placement constraints, see the Designer User's Guide or online help
(available in the software) for Fusion software tools.
Table 2-3 • Array Coordinates
Device
VersaTiles
Min.
Max.
x
y
x
y
AFS090
3
2
98
25
AFS250
3
2
130
49
AFS600
3
4
194
75
AFS1500
3
4
322
123
Memory Rows
Bottom
Top
(x, y)
(x, y)
None
(3, 26)
None
(3, 50)
(3, 2)
(3, 76)
(3, 2)
(3, 124)
Min.
(x, y)
(0, 0)
(0, 0)
(0, 0)
(0, 0)
All
Max.
(x, y)
(101, 29)
(133, 53)
(197, 79)
(325, 129)
(0, 79)
I/O Tile
Top Row (7, 79) to (189, 79)
Bottom Row (5, 78) to (192, 78)
(197, 79)
Memory (3, 77)
Blocks (3, 76)
VersaTile (Core)
(3, 75)
(194, 77) Memory
(194, 76) Blocks
(194, 75)
VersaTile (Core)
VersaTile (Core)
(3, 4)
Memory (3, 3)
Blocks (3, 2)
(194, 4)
VersaTile(Core)
(194, 3) Memory
(194, 2) Blocks
(0, 0)
I/O Tile to Analog Block
Top Row (5, 1) to (168, 1)
Bottom Row (7, 0) to (165, 0)
UJTAG FlashROM
Top Row (169, 1) to (192, 1)
(197, 1)
(197, 0)
Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)};
east side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}.
Figure 2-7 • Array Coordinates for AFS600
2-8
Revision 4