M1AFS600-PQ208 Datasheet, PDF (166/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-77 • Comparison Table for 5 V–Compliant Receiver Scheme
Schem
e
Board Components
1
Two resistors
Speed
Current Limitations
Low to high¹ Limited by transmitter's drive strength
2
Resistor and Zener 3.3 V
Medium Limited by transmitter's drive strength
3
Bus switch
High
N/A
4
Minimum resistor value²
Medium Maximum diode current at 100% duty cycle, signal constantly
R = 47  at T_J = 70°C
R = 150  at T_J = 85°C
R = 420  at T_J = 100°C
at '1'
52.7 mA at T_J =70°C / 10-year lifetime
16.5 mA at T_J = 85°C / 10-year lifetime
5.9 mA at T_J = 100°C / 10-year lifetime
For duty cycles other than 100%, the currents can be
increased by a factor = 1 / (duty cycle).
Example: 20% duty cycle at 70°C
Maximum current = (1 / 0.2) * 52.7 mA = 5 * 52.7 mA = 263.5
mA
Notes:
1. Speed and current consumption increase as the board resistance values decrease.
2. Resistor values ensure I/O diode long-term reliability.
2-150
Revision 4