M1AFS600-PQ208 Datasheet, PDF (119/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
ADC Terminology
Conversion Time
Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a
track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one LSB
of a new input value.
DNL – Differential Non-Linearity
For an ideal ADC, the analog-input levels that trigger any two successive output codes should differ by
one LSB (DNL = 0). Any deviation from one LSB in defined as DNL (Figure 2-83).
Ideal Output
Error = –0.5 LSB
Actual Output
Error = +1 LSB
Input Voltage to Prescaler
Figure 2-83 • Differential Non-Linearity (DNL)
ENOB – Effective Number of Bits
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An
ideal ADC’s error consists only of quantization of noise. As the input frequency increases, the overall
noise (particularly in the distortion components) also increases, thereby reducing the ENOB and SINAD
(also see “Signal-to-Noise and Distortion Ratio (SINAD)”.) ENOB for a full-scale, sinusoidal input
waveform is computed using EQ 12.
ENOB = ^S-----^I--^N-----^A-₆---^D-_.-₀----₂^–----1----^.-⁷----⁶-
EQ 12
FS Error – Full-Scale Error
Full-scale error is the difference between the actual value that triggers that transition to full-scale and the
ideal analog full-scale transition value. Full-scale error equals offset error plus gain error.
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