M1AFS600-PQ208 Datasheet, PDF (241/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
CLK
t_DDROSUD2 t_DDROHD2
Data_F
1
Data_R 6
2
t_DDROSUD1
7
3
t_DDROHD1
8
CLR
Out
t_DDROREMCLR
t_DDROCLR2Q
t_DDROCLKQ
7
2
4
5
9
10
t_DDRORECCLR
8
3
9
4
11
10
Figure 2-145 • Output DDR Timing Diagram
Timing Characteristics
Table 2-182 • Output DDR Propagation Delays
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1 Std. Units
t_DDROCLKQ
Clock-to-Out of DDR for Output DDR
0.70 0.80 0.94 ns
t_DDROSUD1
Data_F Data Setup for Output DDR
0.38 0.43 0.51 ns
t_DDROSUD2
Data_R Data Setup for Output DDR
0.38 0.43 0.51 ns
t_DDROHD1
Data_F Data Hold for Output DDR
0.00 0.00 0.00 ns
t_DDROHD2
Data_R Data Hold for Output DDR
0.00 0.00 0.00 ns
t_DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
0.80 0.91 1.07 ns
t_DDROREMCLR Asynchronous Clear Removal Time for Output DDR
0.00 0.00 0.00 ns
t_DDRORECCLR Asynchronous Clear Recovery Time for Output DDR
0.22 0.25 0.30 ns
t_DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.22 0.25 0.30 ns
t_DDROCKMPWH Clock Minimum Pulse Width High for the Output DDR
0.36 0.41 0.48 ns
t_DDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR
0.32 0.37 0.43 ns
F_DDOMAX
Maximum Frequency for the Output DDR
1404 1232 1048 MHz
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Revision 4
2- 225