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M1AFS600-PQ208 Datasheet, PDF (181/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs
Fusion Family of Mixed Signal FPGAs
D
From Array
tDOUT
DQ
CLK
I/O Interface
tDP
DOUT
PAD
Std
Load
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
tDOUT
(R)
VCC
tDOUT
(F)
D
50%
50%
0V
VCC
DOUT
PAD
50%
Vtrip
tDP
(R)
50%
0V
VOH
Vtrip
VOL
tDP
(F)
Figure 2-117 • Output Buffer Model and Delays (example)
Revision 4
2- 165