M1AFS600-PQ208 Datasheet, PDF (86/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-32 • RAM512X18
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2 –1
Std. Units
t_AS
Address setup time
0.25 0.28 0.33 ns
t_AH
Address hold time
0.00 0.00 0.00 ns
t_ENS
REN, WEN setup time
0.09 0.10 0.12 ns
t_ENH
REN, WEN hold time
0.06 0.07 0.08 ns
t_DS
Input data (WD) setup time
0.18 0.21 0.25 ns
t_DH
Input data (WD) hold time
0.00 0.00 0.00 ns
t_CKQ1
Clock High to new data valid on RD (output retained)
2.16 2.46 2.89 ns
t_CKQ2
Clock High to new data valid on RD (pipelined)
0.90 1.02 1.20 ns
t_C2CRWH1 Address collision clk-to-clk delay for reliable read access after write on 0.50 0.43 0.38 ns
same address—Applicable to Opening Edge
t_C2CWRH1 Address collision clk-to-clk delay for reliable write access after read on 0.59 0.50 0.44 ns
same address— Applicable to Opening Edge
t_RSTBQ1
RESET Low to data out Low on RD (flow-through)
0.92 1.05 1.23 ns
RESET Low to data out Low on RD (pipelined)
0.92 1.05 1.23 ns
t_REMRSTB RESET removal
0.29 0.33 0.38 ns
t_RECRSTB RESET recovery
1.50 1.71 2.01 ns
t_MPWRSTB RESET minimum pulse width
0.21 0.24 0.29 ns
t_CYC
Clock cycle time
3.23 3.68 4.32 ns
F_MAX
Maximum frequency
310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.
2-70
Revision 4