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| M1AFS600-PQ208 Datasheet, PDF (239/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs | |||
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Fusion Family of Mixed Signal FPGAs
CLK
Data
CLR
Out_QF
Out_QR
1
2
3
4
5
tDDRIREMCLR
tDDRICLR2Q1
tDDRICLKQ1
2
tDDRICLR2Q2
3
tDDRISUD
6
tDDRIHD
7
8
9
tDDRIRECCLR
4
6
tDDRICLKQ2
5
7
Figure 2-143 ⢠Input DDR Timing Diagram
Timing Characteristics
Table 2-180 ⢠Input DDR Propagation Delays
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
â2
â1
Std.
Units
tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR
0.39 0.44 0.52
ns
tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR
0.27 0.31 0.37
ns
tDDRISUD
Data Setup for Input DDR
0.28 0.32 0.38
ns
tDDRIHD
Data Hold for Input DDR
0.00 0.00 0.00
ns
tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR
0.57
0.65
0.76
ns
tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR
0.46 0.53 0.62
ns
tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR
0.00 0.00 0.00
ns
tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR
0.22 0.25 0.30
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.22 0.25 0.30
ns
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR
0.36 0.41 0.48
ns
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR
0.32 0.37 0.43
ns
FDDRIMAX
Maximum Frequency for Input DDR
1404 1232 1048 MHz
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Revision 4
2- 223
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