M1AFS600-PQ208 Datasheet, PDF (127/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
along with the use of the active bipolar prescaler, current monitor, or temperature monitor, the minimum
sample time(s) for each must be obeyed. EQ 19 can be used to determine the appropriate value of STC.
You can calculate the minimum actual acquisition time by using EQ 16:
VOUT = VIN(1 – e–^t/RC)
EQ 16
For 0.5 LSB gain error, VOUT should be replaced with (VIN –(0.5 × LSB Value)):
(VIN – 0.5 × LSB Value) = VIN(1 – e–^t/RC)
EQ 17
where VIN is the ADC reference voltage (VREF)
Solving EQ 17:
t = RC x ln (VIN / (0.5 x LSB Value))
EQ 18
where R = Z_INAD + R_SOURCE and C = C_INAD.
Calculate the value of STC by using EQ 19.
t_SAMPLE = (2 + STC) x (1 / ADCCLK) or t_SAMPLE = (2 + STC) x (ADC Clock Period)
EQ 19
where ADCCLK = ADC clock frequency in MHz.
t_SAMPLE = 0.449 µs from bit resolution in Table 2-44.
ADC Clock frequency = 10 MHz or a 100 ns period.
STC = (t_SAMPLE / (1 / 10 MHz)) – 2 = 4.49 – 2 = 2.49.
You must round up to 3 to accommodate the minimum sample time.
Table 2-44 • Acquisition Time Example with VAREF = 2.56 V
Resolution
VIN = 2.56V, R = 4K (R_SOURCE ~ 0), C = 18 pF
LSB Value (mV)
Min. Sample/Hold Time for 0.5 LSB (µs)
8
10
0.449
10
2.5
0.549
12
0.625
0.649
Table 2-45 • Acquisition Time Example with VAREF = 3.3 V
Resolution
VIN = 3.3V, R = 4K (R_SOURCE ~ 0), C = 18 pF
LSB Value (mV)
Min. Sample/Hold time for 0.5 LSB (µs)
8
12.891
0.449
10
3.223
0.549
12
0.806
0.649
Sample Phase
A conversion is performed in three phases. In the first phase, the analog input voltage is sampled on the
input capacitor. This phase is called sample phase. During the sample phase, the output signals BUSY
and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the analog signal. The
sample time can be controlled by input signals STC[7:0]. The sample time can be calculated by EQ 20.
When controlling the sample time for the ADC along with the use of Prescaler or Current Monitor or
Temperature Monitor, the minimum sample time for each must be obeyed. Refer to Table 2-46 on
page 2-112 and the "Acquisition Time or Sample Time Control" section on page 2-110
t_sample = 2 + STC  t_ADCCLK
STC: Sample Time Control value (0–255)
t_SAMPLE is the sample time
EQ 20
Revision 4
2- 111