M1AFS600-PQ208 Datasheet, PDF (165/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Solution 3
The board-level design must ensure that the reflected waveform at the pad does not exceed limits
provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used
for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-105. Relying on the
diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 3
Fusion I/O Input
5.5 V
Off-Chip
Bus
Switch
IDTQS32X23
On-Chip
3.3 V
5.5 V
Requires a bus switch on the board,
LVTTL/LVCMOS 3.3 V I/Os.
Figure 2-105 • Solution 3
Solution 4
Solution 4
Fusion I/O Input
Off-Chip
5.5 V
On-Chip
2.5 V On-Chip
Clamp
Diode
2.5 V
Rext1
Figure 2-106 • Solution 4
Requires one board resistor.
Available for LVCMOS 2.5 V / 5.0 V.
Revision 4
2- 149