M1AFS600-PQ208 Datasheet, PDF (138/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-49 • Analog Channel Specifications (continued)
Commercial Temperature Range Conditions, T_J = 85°C (unless noted otherwise),
Typical: VCC33A = 3.3 V, VCC = 1.5 V
Parameter
Description
Condition
Min. Typ.
Max.
Units
Digital Input using Analog Pads AV, AC and AT
VIND^2,3
Input Voltage
Refer to Table 3-2 on page 3-3
VHYSDIN
Hysteresis
0.3
V
VIHDIN
Input High
1.2
V
VILDIN
Input Low
0.9
V
VMPWDIN
Minimum Pulse With
50
ns
F_DIN
ISTBDIN
Maximum Frequency
Input Leakage Current
10
MHz
2
µA
IDYNDIN
Dynamic Current
20
µA
t_INDIN
Input Delay
Gate Driver Output Using Analog Pad AG
10
ns
VG
Voltage Range
Refer to Table 3-2 on page 3-3
IG
Output Current Drive High Current Mode⁶ at 1.0 V
±20
mA
Low Current Mode: ±1 µA
0.8 1.0
1.3
µA
Low Current Mode: ±3 µA
2.0 2.7
3.3
µA
Low Current Mode: ± 10 µA
7.4 9.0
11.5
µA
Low Current Mode: ± 30 µA
21.0 27.0
32.0
µA
IOFFG
F_G
Maximum Off Current
Maximum switching rate High Current Mode⁶ at 1.0 V, 1
k resistive load
100
nA
1.3
MHz
Low Current Mode:
3
KHz
±1 µA, 3 M resistive load
Low Current Mode:
7
KHz
±3 µA, 1 M resistive load
Low Current Mode:
25
KHz
±10 µA, 300 k resistive load
Low Current Mode:
78
KHz
±30 µA, 105 k resistive load
Notes:
1. VRSM is the maximum voltage drop across the current sense resistor.
2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no
reliability concern on digital inputs as long as VIND does not exceed these limits.
3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.
4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance
allowed across the AT pins is 500 pF.
5. The temperature offset is a fixed positive value.
6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on
voltage on the pad.
7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer
to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s
Guide.
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