M1AFS600-PQ208 Datasheet, PDF (157/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-100 for a
simplified representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in Figure 2-100) between
registers to implement single or differential data transmission to and from the FPGA core. The Designer
software sets these switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input
register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O
register combining must satisfy some rules.
I/O / Q0
1
Input
Reg
To FPGA Core
CLR/PRE
I/O / Q1
3
Input
ICE ^Reg
CLR/PRE
I/O / ICLK
2
Input
Reg
Y
Pull-Up/Down
Resistor Control
PAD
Signal Drive Strength
and Slew-Rate Control
A
E = Enable Pin
I/O / D0
4
OCE
Output
Reg
From FPGA Core
I/O / D1 / ICE
CLR/PRE
5
ICE _Output
Reg
I/O / OCLK
I/O / OE
I/O / CLR or I/O / PRE / OCE
CLR/PRE
6
OCE ^Output
Enable
Reg
CLR/PRE
Note: Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on
page 2-142 for more information).
Figure 2-100 • I/O Block Logical Representation
Revision 4
2- 141