M1AFS600-PQ208 Datasheet, PDF (329/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Revision
Advance v0.8
(continued)
Advance v0.7
(January 2007)
Advance v0.6
(October 2006)
Changes
The voltage range in the "VPUMP Programming Supply Voltage" section was
updated. The parenthetical reference to "pulled up" was removed from the
statement, "VPUMP can be left floating or can be tied (pulled up) to any voltage
between 0 V and 3.6 V."
The "ATRTNx Temperature Monitor Return" section was updated with information
about grounding and floating the pin.
The following text was deleted from the "VREF I/O Voltage Reference" section: (all
digital I/O).
The "NCAP Negative Capacitor" section and "PCAP Positive Capacitor" section
were updated to include information about the type of capacitor that is required to
connect the two.
1 µF was changed to 100 pF in the "XTAL1 Crystal Oscillator Circuit Input".
The "Programming" section was updated to include information about V_CCOSC.
The VMV pins have now been tied internally with the V_CCI pins.
The AFS090"108-Pin QFN" table was updated.
The AFS090 and AFS250 devices were updated in the "108-Pin QFN" table.
The AFS250 device was updated in the "208-Pin PQFP" table.
The AFS600 device was updated in the "208-Pin PQFP" table.
The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the "256-Pin
FBGA" table.
The AFS600 and AFS1500 devices were updated in the "484-Pin FBGA" table.
The AFS600 device was updated in the "676-Pin FBGA" table.
The AFS1500 digital I/O count was updated in the "Fusion Family" table.
The AFS1500 digital I/O count was updated in the "Package I/Os: Single-/Double-
Ended (Analog)" table.
The second paragraph of the "PLL Macro" section was updated to include
information about POWERDOWN.
The description for bit 0 was updated in Table 2-17 · RTC Control/Status Register.
3.9 was changed to 7.8 in the "Crystal Oscillator (Xtal Osc)" section.
All function descriptions in Table 2-18 · Signals for VRPSM Macro.
In Table 2-19 • Flash Memory Block Pin Names, the RD[31:0] description was
updated.
The "RESET" section was updated.
The "RESET" section was updated.
Table 2-35 • FIFO was updated.
The VAREF function description was updated in Table 2-36 • Analog Block Pin
Description.
The "Voltage Monitor" section was updated to include information about low power
mode and sleep mode.
The text in the "Current Monitor" section was changed from 2 mV to 1 mV.
The "Gate Driver" section was updated to include information about forcing 1 V on
the drain.
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Revision 4
5- 13