M1AFS600-PQ208 Datasheet, PDF (130/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Timing Diagrams
SYSCLK
ADCRESET
TVC[7:0]
CALIBRATE
t_CAL = 3,840 t_ADCCLK*
t_RECCLR t_REMCLR
t_SUTVC t_HDTVC
t_CK2QCAL
t_CK2QCAL
Note: *Refer to EQ 15 on page 2-110 for the calculation on the period of ADCCLK, t_ADCCLK.
Figure 2-89 • Power-Up Calibration Status Signal Timing Diagram
SYSCLK
ADCSTART
MODE[3:0]
TVC[7:0]
STC[7:0]
t_MINSYSCLK
t_SUADCSTART t_HDADCSTART
t_SUMODE t_HDMODE
t_SUTVC t_HDTVC
t_SUSTC t_HDSTC
t_SUVAREFSEL t_HDVAREFSEL
VAREF
CHNUMBER[7:0]
Figure 2-90 • Input Setup Time
t_SUCHNUM t_HDCHNUM
t_MPWSYSCLK
2-114
Revision 4