M1AFS600-PQ208 Datasheet, PDF (102/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input
signals. Figure 2-67 shows the path through the Analog Quad for a signal that is to be prescaled prior to
conversion. The ADC internal reference voltage and the prescaler factors were selected to make both
prescaling and postscaling of the signals easy binary calculations (refer to Table 2-57 on page 2-133 for
details). When an analog input pad is configured with a prescaler, there will be a 1 M resistor to ground.
This occurs even when the device is in power-down mode. In low power standby or sleep mode (VCC is
OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, analog inputs are pulled down to
ground through a 1 M resistor. The gate driver output is floating (or tristated), and there is no extra
current on VCC33A.
These scaling factors hold true whether the particular pad is configured to accept a positive or negative
voltage. Note that whereas the AV and AC pads support the same prescaling factors, the AT pad
supports a reduced set of prescaling factors and supports positive voltages only.
Typical scaling factors are given in Table 2-57 on page 2-133, and the gain error (which contributes to the
minimum and maximum) is in Table 2-49 on page 2-120.
Off-Chip
Pads
On-Chip
AV
Voltage
Monitor Block
Prescaler
AC
Current
Monitor Block
AG
Gate
Driver
AT
Temperature
Monitor Block
Analog Quad
Prescaler
Prescaler
Digital
Input
Digital
Input
Current
Monitor / Instr
Amplifier
Power
MOSFET
Gate Driver
To FPGA
(DAVOUTx)
To Analog MUX
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To Analog MUX
Figure 2-67 • Analog Quad Prescaler Input Configuration
Digital
Input
Temperature
Monitor
To FPGA
(DATOUTx)
To Analog MUX
2-86
Revision 4