M1AFS600-PQ208 Datasheet, PDF (106/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the AB
macro must be asserted low for at least t_CMSLO in order to discharge the previous measurement. Then
CMSTB must be asserted high for at least t_CMSET prior to asserting the ADCSTART signal. The CMSTB
must remain high until after the SAMPLE signal is de-asserted by the AB macro. Note that the minimum
sample time cannot be less than t_CMSHI. Figure 2-71 shows the timing diagram of CMSTB in relationship
with the ADC control signals.
CMSTBx
VADC
t_CMSLO
ADCSTART
t_CMSHI
t_CMSET
ADCSTART can be asserted
after this point to start ADC
sampling.
Figure 2-71 • Timing Diagram for Current Monitor Strobe
Figure 2-72 illustrates positive current monitor operation. The differential voltage between AV and AC
goes into the 10× amplifier and is then converted by the ADC. For example, a current of 1.5 A is drawn
from a 10 V supply and is measured by the voltage drop across a 0.050  sense resistor, The voltage
drop is amplified by ten times by the amplifier and then measured by the ADC. The 1.5 A current creates
a differential voltage across the sense resistor of 75 mV. This becomes 750 mV after amplification. Thus,
the ADC measures a current of 1.5 A as 750 mV. Using an ADC with 8-bit resolution and VAREF of 2.56
V, the ADC result is decimal 75. EQ 3 shows how to compute the current from the ADC result.
I = ADC  V_AREF  10  2^N  R_sense
EQ 3
where
I is the current flowing through the sense resistor
ADC is the result from the ADC
VAREF is the Reference voltage
N is the number of bits
Rsense is the resistance of the sense resistor
2-90
Revision 4