M1AFS600-PQ208 Datasheet, PDF (182/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
t_EOUT
DQ
E
CLK
t_ZL, t_ZH, t_HZ, t_LZ, t_ZLS, t_ZHS
DQ
D
CLK
DOUT
EOUT
PAD
I/O Interface
D
E
EOUT
PAD
50%
t_{EOUT (R)}
50%
t_ZL
V_{trip VOL}
t_EOUT = MAX(t_EOUT (R). t_EOUT (F))
VCC
50%
t_{EOUT (F)}
50%
t_HZ
90% VCCI
VCC
50%
t_ZH
VCC
VCCI
V_trip
50%
t_LZ
10% VCCI
VCC
D
E ^50%
EOUT
PAD
t_EOUT
(R)
50%
VCC
50%
t_ZLS
V_{trip VOL}
t_{EOUT (F)}
50%
VOH
VCC
50%
t_ZHS
V_trip
Figure 2-118 • Tristate Output Buffer Timing Model and Delays (example)
2-166
Revision 4