M1AFS600-PQ208 Datasheet, PDF (131/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Standard Conversion
Fusion Family of Mixed Signal FPGAs
t _SAMPLE1
SYSCLK
t t _{SUADCSTART HDADCSTART}
ADCSTART
t _CK2QBUSY
BUSY
t _CK2QSAMPLE
SAMPLE
t _CONV2
DATAVALID
ADC_RESULT[11:0]
t _DATA2START3
t _CK2QVAL
t _CK2QVAL
t _CLK2RESULT
1^st Sample Result
2^nd Sample Result
Notes:
1. Refer to EQ 20 on page 2-111 for the calculation on the sample time, t_SAMPLE.
2. See EQ 23 on page 2-112 for calculation of the conversion time, t_CONV.
3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period
Figure 2-91 • Standard Conversion Status Signal Timing Diagram
Intra-Conversion
SYSCLK
ADCRESET
ADCSTART
BUSY
SAMPLE
DATAVALID
CALIBRATE
t_CLR2QVAL
t_CK2QCAL
t_CK2QBUSY
t_CK2QSAMPLE t_CK2QSAMPLE
t_CONV*
t_CK2QVAL
t_CK2QCAL
Interrupts Power-Up Calibration
Resumes Power-Up Calibration
Note: *t_CONV represents the conversion time of the second conversion. See EQ 23 on page 2-112 for calculation of the
conversion time, t_CONV.
Figure 2-92 • Intra-Conversion Timing Diagram
Revision 4
2- 115