M1AFS600-PQ208 Datasheet, PDF (94/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Timing Characteristics
Table 2-35 • FIFO
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
t_CKQ2
t_RCKEF
t_WCKFF
t_CKAF
t_RSTFG
t_RSTAF
t_RSTBQ
REN, WEN Setup time
REN, WEN Hold time
BLK Setup time
BLK Hold time
Input data (WD) Setup time
Input data (WD) Hold time
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost-Empty/Full Flag Valid
RESET Low to Data out Low on RD (flow-through)
RESET Low to Data out Low on RD (pipelined)
1.34
1.52
1.79
ns
0.00
0.00
0.00
ns
0.19
0.22
0.26
ns
0.00
0.00
0.00
ns
0.18
0.21
0.25
ns
0.00
0.00
0.00
ns
2.17
2.47
2.90
ns
0.94
1.07
1.26
ns
1.72
1.96
2.30
ns
1.63
1.86
2.18
ns
6.19
7.05
8.29
ns
1.69
1.93
2.27
ns
6.13
6.98
8.20
ns
0.92
1.05
1.23
ns
0.92
1.05
1.23
ns
t_REMRSTB
RESET Removal
0.29
0.33
0.38
ns
t_RECRSTB
RESET Recovery
1.50
1.71
2.01
ns
t_MPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
t_CYC
Clock Cycle time
3.23
3.68
4.32
ns
F_MAX
Maximum Frequency for FIFO
310
272
231
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
2-78
Revision 4