M1AFS600-PQ208 Datasheet, PDF (318/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Datasheet Information
Revision
Revision 3
(continued)
Revision 2
(March 2012)
Changes
The drive strength, IOL, and IOH for 3.3 V GTL and 2.5 V GTL were changed from
25 mA to 20 mA in the following tables (SAR 37373):
Table 2-86 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions,
Table 2-92 • Summary of I/O Timing Characteristics – Software Default Settings
Table 2-96 • I/O Output Buffer Maximum Resistances 1
Table 2-138 • Minimum and Maximum DC Input and Output Levels
Table 2-141 • Minimum and Maximum DC Input and Output Levels
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34800):
"It uses a 5 V–tolerant input buffer and push-pull output buffer."
Corrected the inadvertent error in maximum values for LVPECL VIH and VIL and
revised them to "3.6" in Table 2-171 • Minimum and Maximum DC Input and Output
Levels, making these consistent with Table 3-1 • Absolute Maximum Ratings, and
Table 3-4 • Overshoot and Undershoot Limits 1 (SAR 37687).
The maximum frequency for global clock parameter was removed from Table 2-5 •
AFS1500 Global Resource Timing through Table 2-8 • AFS090 Global Resource
Timing because a frequency on the global is only an indication of what the global
network can do. There are other limiters such as the SRAM, I/Os, and PLL.
SmartTime software should be used to determine the design frequency (SAR
36955).
The phrase "without debug" was removed from the "Soft ARM Cortex-M1 Fusion
Devices (M1)" section (SAR 21390).
The "In-System Programming (ISP) and Security" section, "Security" section, "Flash
Advantages" section, and "Security" section were revised to clarify that although no
existing security measures can give an absolute guarantee, Microsemi FPGAs
implement the best security available in the industry (SAR 34679).
The Y security option and Licensed DPA Logo was added to the "Product Ordering
Codes" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR
34721).
The "Specifying I/O States During Programming" section is new (SAR 34693).
The following information was added before Figure 2-17 • XTLOSC Macro:
In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be
connected to GND and the XTAL2 pin should be left floating (SAR 24119).
Table 2-12 • Fusion CCC/PLL Specification was updated. A note was added
indicating that when the CCC/PLL core is generated by Microsemi core generator
software, not all delay values of the specified delay increments are available (SAR
34814).
A note was added to Figure 2-27 • Real-Time Counter System (not all the signals are
shown for the AB macro) stating that the user is only required to instantiate the
VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator
to be different from the default, or employ user logic to shut the voltage regulator off
(SAR 21773).
Page
2-167
2-170
2-172
2-202
2-203
2-184
2-214
2-17 to
2-18
I
I, 1-2,
2-231
III
1-8
2-21
2-30
2-33
5-2
Revision 4