M1AFS600-PQ208 Datasheet, PDF (231/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Preset
Data
Enable
CLK
XD
PRE
XD
Q
C _DFN1E1P1
EY
X
X
E
B
X
A
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive Edge Triggered
CLKBUF
Core
Array
INBUF
Data_out
F
X
G
X
H
X
I
X
J
X
K
X
L
X
DOUT
PRE
D
QX
DFN1E1P1
E
X
EOUT
PRE
D
Q
DFN1E1P1
E
INBUF
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive Edge Triggered
Figure 2-137 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Revision 4
2- 215