M1AFS600-PQ208 Datasheet, PDF (234/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-175 • Parameter Definitions and Measuring Nodes
Parameter Name
Parameter Definition
t_{O C L K Q}
Clock-to-Q of the Output Data Register
t_OSUD
Data Setup Time for the Output Data Register
t_OHD
Data Hold Time for the Output Data Register
t_OSUE
Enable Setup Time for the Output Data Register
t_OHE
Enable Hold Time for the Output Data Register
t_OCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
t_OREMCLR
Asynchronous Clear Removal Time for the Output Data Register
t_ORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
t_OECLKQ
Clock-to-Q of the Output Enable Register
t_OESUD
Data Setup Time for the Output Enable Register
t_OEHD
Data Hold Time for the Output Enable Register
t_OESUE
Enable Setup Time for the Output Enable Register
t_OEHE
Enable Hold Time for the Output Enable Register
t_OECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
t_OEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
t_OERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
t_ICLKQ
Clock-to-Q of the Input Data Register
t_ISUD
Data Setup Time for the Input Data Register
t_IHD
Data Hold Time for the Input Data Register
t_ISUE
Enable Setup Time for the Input Data Register
t_IHE
Enable Hold Time for the Input Data Register
t_ICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
t_IREMCLR
Asynchronous Clear Removal Time for the Input Data Register
t_IRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 2-138 on page 2-217 for more information.
Measuring Nodes
(from, to)*
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
JJ, HH
KK, HH
KK, HH
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
2-218
Revision 4