M1AFS600-PQ208 Datasheet, PDF (268/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

DC and Power Characteristics
Power per I/O Pin
Table 3-12 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings
VCCI (V)
Static Power
PDC7 (mW)¹
Applicable to Pro I/O Banks
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
–
3.3 V LVTTL/LVCMOS – Schmitt trigger
3.3
–
2.5 V LVCMOS
2.5
–
2.5 V LVCMOS – Schmitt trigger
2.5
–
1.8 V LVCMOS
1.8
–
1.8 V LVCMOS – Schmitt trigger
1.8
–
1.5 V LVCMOS (JESD8-11)
1.5
–
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.5
–
3.3 V PCI
3.3
–
3.3 V PCI – Schmitt trigger
3.3
–
3.3 V PCI-X
3.3
–
3.3 V PCI-X – Schmitt trigger
3.3
–
Voltage-Referenced
3.3 V GTL
3.3
2.90
2.5 V GTL
2.5
2.13
3.3 V GTL+
3.3
2.81
2.5 V GTL+
2.5
2.57
HSTL (I)
1.5
0.17
HSTL (II)
1.5
0.17
SSTL2 (I)
2.5
1.38
SSTL2 (II)
2.5
1.38
SSTL3 (I)
3.3
3.21
SSTL3 (II)
3.3
3.21
Differential
LVDS
2.5
2.26
LVPECL
3.3
5.71
Notes:
1. PDC7 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCC and VCCI.
Dynamic Power
PAC9 (µW/MHz)²
17.39
25.51
5.76
7.16
2.72
2.80
2.08
2.00
18.82
20.12
18.82
20.12
8.23
4.78
4.14
3.71
2.03
2.03
4.48
4.48
9.26
9.26
1.50
2.17
3-18
Revision 4