M1AFS600-PQ208 Datasheet, PDF (60/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Flash Memory Block Diagram
A simplified diagram of the flash memory block is shown in Figure 2-33.
RD[31:0]
Output
MUX
ECC
Logic
Page Buffer = 8 Blocks
Plus AUX Block
Flash Array = 64 Sectors
WD[31 :0]
Block Buffer
(128 bits)
ADDDR[17:0]
DATAWIDTH[1:0]
REN
READNEXT
PAGESTATUS
WEN
ERASEPAGE
PROGRAM
SPAREPAGE
AUXBLOCK
UNPROTECTPAGE
OVERWRITEPAGE
DISCARDPAGE
OVERWRITEPROTECT
PAGELOSSPROTECT
PIPE
LOCKREQUEST
CLK
RESET
STATUS[1:0]
BUSY
Control
Logic
Figure 2-33 • Flash Memory Block Diagram
The logic consists of the following sub-blocks:
• Flash Array
Contains all stored data. The flash array contains 64 sectors, and each sector contains 33 pages
of data.
• Page Buffer
A page-wide volatile register. A page contains 8 blocks of data and an AUX block.
• Block Buffer
Contains the contents of the last block accessed. A block contains 128 data bits.
• ECC Logic
The FB stores error correction information with each block to perform single-bit error correction and
double-bit error detection on all data blocks.
2-44
Revision 4