M1AFS600-PQ208 Datasheet, PDF (35/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Clocking Resources
The Fusion family has a robust collection of clocking peripherals, as shown in the block diagram in
Figure 2-16. These on-chip resources enable the creation, manipulation, and distribution of many clock
signals. The Fusion integrated RC oscillator produces a 100 MHz clock source with no external
components. For systems requiring more precise clock signals, the Fusion family supports an on-chip
crystal oscillator circuit. The integrated PLLs in each Fusion device can use the RC oscillator, crystal
oscillator, or another on-chip clock signal as a source. These PLLs offer a variety of capabilities to modify
the clock source (multiply, divide, synchronize, advance, or delay). Utilizing the CCC found in the popular
ProASIC3 family, Fusion incorporates six CCC blocks. The CCCs allow access to Fusion global and local
clock distribution nets, as described in the "Global Resources (VersaNets)" section on page 2-12.
Off-Chip On-Chip
GNDOSC
VCCOSC
100 MHz
RC Oscillator
Clock Out to FPGA Core through CCC
External
Crystal
or
External
RC
XTAL1
XTAL2
Crystal Oscillator
Clock I/Os
From FPGA Core
Xtal Clock
GLINT
PLL/ GLA
CCC _GLC
Figure 2-16 • Fusion Clocking Options
NGMUX
To Core
CLKOUT
Revision 4
2- 19