M1AFS600-PQ208 Datasheet, PDF (232/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-174 • Parameter Definitions and Measuring Nodes
Parameter
Name
Parameter Definition
t_OCLKQ
Clock-to-Q of the Output Data Register
t_OSUD
Data Setup Time for the Output Data Register
t_OHD
Data Hold Time for the Output Data Register
t_OSUE
Enable Setup Time for the Output Data Register
t_OHE
Enable Hold Time for the Output Data Register
t_OPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
t_OREMPRE
Asynchronous Preset Removal Time for the Output Data Register
t_ORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
t_OECLKQ
Clock-to-Q of the Output Enable Register
t_OESUD
Data Setup Time for the Output Enable Register
t_OEHD
Data Hold Time for the Output Enable Register
t_OESUE
Enable Setup Time for the Output Enable Register
t_OEHE
Enable Hold Time for the Output Enable Register
t_OEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
t_OEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
t_OERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
t_ICLKQ
Clock-to-Q of the Input Data Register
t_ISUD
Data Setup Time for the Input Data Register
t_IHD
Data Hold Time for the Input Data Register
t_ISUE
Enable Setup Time for the Input Data Register
t_IHE
Enable Hold Time for the Input Data Register
t_IPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
t_IREMPRE
Asynchronous Preset Removal Time for the Input Data Register
t_IRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
Note: *See Figure 2-137 on page 2-215 for more information.
Measuring Nodes
(from, to)*
H, DOUT
F, H
F, H
G, H
G, H
L,DOUT
L, H
L, H
H, EOUT
J, H
J, H
K, H
K, H
I, EOUT
I, H
I, H
A, E
C, A
C, A
B, A
B, A
D, E
D, A
D, A
2-216
Revision 4