M1AFS600-PQ208 Datasheet, PDF (223/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output
buffer.
Table 2-153 • Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL¹ IIH²
Drive Strength
15 mA³
Min.
V
–0.3
Max.
V
Min.
V
VREF – 0.1 VREF + 0.1
Max.
V
3.6
Max.
V
0.4
Min.
V
mA mA
VCCI – 0.4 15 15
Max.
mA³
55
Max.
mA³ µA⁴ µA⁴
66 10 10
Note:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Output drive strength is below JEDEC specification.
VTT
HSTL
Class II ₂₅
Test Point
20 pF
Figure 2-129 • AC Loading
Table 2-154 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V)
VREF – 0.1
VREF + 0.1
0.75
0.75
0.75
C_LOAD (pF)
20
Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.
Timing Characteristics
Table 2-155 • HSTL Class II
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
Speed
Grade t_DOUT t_DP
t_DIN
t_PY
t_EOUT
t_ZL
t_ZH
t_LZ
Std.
0.66 3.02 0.04 2.12 0.43 3.08 2.71
t_HZ
t_ZLS
t_ZHS
5.32 4.95
Units
ns
–1
0.56 2.57 0.04 1.81 0.36 2.62 2.31
4.52 4.21
ns
–2
0.49 2.26 0.03 1.59 0.32 2.30 2.03
3.97 3.70
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Revision 4
2- 207