M1AFS600-PQ208 Datasheet, PDF (330/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Datasheet Information
Revision
Advance v0.6
(continued)
Changes
The "Analog-to-Digital Converter Block" section was updated with the following
statement:
"All results are MSB justified in the ADC."
The information about the ADCSTART signal was updated in the "ADC Description"
section.
Table 2-46 · Analog Channel Specifications was updated.
Table 2-47 · ADC Characteristics in Direct Input Mode was updated.
Table 2-51 • ACM Address Decode Table for Analog Quad was updated.
In Table 2-53 • Analog Quad ACM Byte Assignment, the Function and Default
Setting for Bit 6 in Byte 3 was updated.
The "Introduction" section was updated to include information about digital inputs,
outputs, and bibufs.
In Table 2-69 • Fusion Pro I/O Features, the programmable delay descriptions were
updated for the following features:
Single-ended receiver
Voltage-referenced differential receiver
LVDS/LVPECL differential receiver features
The "User I/O Naming Convention" section was updated to include "V" and "z"
descriptions
The "VCC33PMP Analog Power Supply (3.3 V)" section was updated to include
information about avoiding high current draw.
The "VCCNVM Flash Memory Block Power Supply (1.5 V)" section was updated to
include information about avoiding high current draw.
The "VMVx I/O Supply Voltage (quiet)" section was updated to include this
statement: VMV and VCCI must be connected to the same power supply and V_CCI
pins within a given I/O bank.
The "PUB Push Button" section was updated to include information about leaving
the pin floating if it is not used.
The "PTBASE Pass Transistor Base" section was updated to include information
about leaving the pin floating if it is not used.
The "PTEM Pass Transistor Emitter" section was updated to include information
about leaving the pin floating if it is not used.
The heading was incorrect in the "208-Pin PQFP" table. It should be AFS250 and not
AFS090.
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Revision 4