M1AFS600-PQ208 Datasheet, PDF (233/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Data
Enable
CLK
CLR
DOUT
Y
D
Q
Core
Array
Data_out ^FF
D
Q
CC
DFN1E1C1 ^EE
DFN1E1C1
GG
E
E
EOUT
BB
CLR
CLR
LL
HH
AA
DD
Data Input I/O Register with
Active High Enable
Active High Clear
Positive Edge Triggered
INBUF
JJ
D
Q
DFN1E1C1
KK
E
CLR
INBUF CLKBUF
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive Edge Triggered
Figure 2-138 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Revision 4
2- 217