M1AFS600-PQ208 Datasheet, PDF (251/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

3 – DC and Power Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on
page 3-3.
Table 3-1 • Absolute Maximum Ratings
Symbol
Parameter
Commercial
Industrial
Units
VCC
DC core supply voltage
–0.3 to 1.65
–0.3 to 1.65
V
VJTAG
JTAG DC voltage
–0.3 to 3.75
–0.3 to 3.75
V
VPUMP
Programming voltage
–0.3 to 3.75
–0.3 to 3.75
V
VCCPLL Analog power supply (PLL)
–0.3 to 1.65
–0.3 to 1.65
V
VCCI
VI
DC I/O output buffer supply voltage
I/O input voltage ¹
VCC33A +3.3 V power supply
VCC33PMP +3.3 V power supply
–0.3 to 3.75
–0.3 to 3.75
V
–0.3 V to 3.6 V (when I/O hot insertion mode is V
enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever
voltage is lower (when I/O hot-insertion mode is
disabled)
–0.3 to 3.75 ²
–0.3 to 3.75 ²
V
–0.3 to 3.75 ²
–0.3 to 3.75 ²
V
VAREF
Voltage reference for ADC
–0.3 to 3.75
–0.3 to 3.75
V
VCC15A Digital power supply for the analog system
–0.3 to 1.65
–0.3 to 1.65
V
VCCNVM Embedded flash power supply
–0.3 to 1.65
–0.3 to 1.65
V
VCCOSC Oscillator power supply
–0.3 to 3.75
–0.3 to 3.75
V
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4.
2. Analog data not valid beyond 3.65 V.
3. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on
voltage on the pad.
4. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits
refer to Table 3-2 on page 3-3.
Revision 4
3-1