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M1AFS600-PQ208 Datasheet, PDF (179/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs
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User I/O Characteristics
Timing Model
Fusion Family of Mixed Signal FPGAs
Combinational Cell
Y
tPD = 0.56 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
LVPECL (Pro IO banks)
tPD = 0.49 ns
tDp = 1.60 ns
Combinational Cell
I/O Module
(Non-Registered)
LVPECL
(Pro IO Banks)
I/O Module
(Registered)
tPY = 1.22 ns
DQ
Input LVTTL/LVCMOS
3.3 V (Pro IO banks)
tICLKQ = 0.24 ns
tISUD = 0.26 ns
tPY = 0.90 ns
I/O Module
(Non-Registered)
Y
tPD = 0.87 ns
Combinational Cell
LVTTL/LVCMOS 3.3 V (Pro I/O banks)
tDP = 2.74 ns
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Y
LVTTL/LVCMOS 3.3 V (Pro I/O banks)
tDP = 2.39 ns
Output drive strength = 24 mA
High slew rate
tPD = 0.51 ns
Combinational Cell
I/O Module
(Non-Registered)
Y
tPD = 0.47 ns
LVCMOS 1.5 V (Pro IO banks)
tDP = 3.30 ns
Output drive strength = 12 mA
High slew
Register Cell Combinational Cell
DQ
Y
tPD = 0.47 ns
Register Cell
DQ
I/O Module
(Registered)
DQ
GTL+ 3.3 V
tDP = 1.53 ns
LVDS,
BLVDS,
M-LVDS (Pro IO Banks)
tPY = 1.36 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
Input LVTTL/LVCMOS
3.3 V (Pro IO banks)
tCLKQ = 0.55 ns
tSUD = 0.43 ns
IInput LVTTL/LVCMOS
3.3 V (Pro IO banks)
tOCLKQ = 0.59 ns
tOSUD = 0.31 ns
tPY = 0.90 ns
tPY = 0.90 ns
Figure 2-115 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C),
Worst-Case VCC = 1.425 V
Revision 4
2- 163
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