M1AFS600-PQ208 Datasheet, PDF (85/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Timing Characteristics
Table 2-31 • RAM4K9
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2 –1
Std. Units
t_AS
t_AH
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
Address setup time
Address hold time
REN, WEN setup time
REN, WEN hold time
BLK setup time
BL hold time
Input data (DIN) setup time
Input data (DIN) hold time
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
0.25 0.28 0.33 ns
0.00 0.00 0.00 ns
0.14 0.16 0.19 ns
0.10 0.11 0.13 ns
0.23 0.27 0.31 ns
0.02 0.02 0.02 ns
0.18 0.21 0.25 ns
0.00 0.00 0.00 ns
1.79 2.03 2.39 ns
2.36 2.68 3.15 ns
t_CKQ2
Clock High to new data valid on DOUT (pipelined)
0.89 1.02 1.20 ns
t_C2CWWH1 Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23 ns
address—Applicable to Rising Edge
t_C2CRWH1 Address collision clk-to-clk delay for reliable read access after write on 0.45 0.38 0.34 ns
same address—Applicable to Opening Edge
t_C2CWRH1 Address collision clk-to-clk delay for reliable write access after read on 0.49 0.42 0.37 ns
same address— Applicable to Opening Edge
t_RSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to Data Out Low on DOUT (pipelined)
0.92 1.05 1.23 ns
0.92 1.05 1.23 ns
t_REMRSTB RESET removal
0.29 0.33 0.38 ns
t_RECRSTB RESET recovery
1.50 1.71 2.01 ns
t_MPWRSTB RESET minimum pulse width
0.21 0.24 0.29 ns
t_CYC
Clock cycle time
3.23 3.68 4.32 ns
F_MAX
Maximum frequency
310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.
Revision 4
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