M1AFS600-PQ208 Datasheet, PDF (226/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-162 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL¹ IIH²
Drive
Strength
Min.
V
Max.
V
Min.
V
Max. Max.
V
V
Min.
V
Max. Max.
mA mA mA³ mA³ µA⁴ µA⁴
14 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 54 51 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
SSTL3 ^VTT
Class I ₅₀
Test Point
25
30 pF
Figure 2-132 • AC Loading
Table 2-163 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V)
VREF – 0.2
VREF + 0.2
1.5
1.5
1.485
Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.
C_LOAD (pF)
30
Timing Characteristics
Table 2-164 • SSTL3 Class I
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade
t_DOUT t_DP
t_DIN
t_PY
t_EOUT
t_ZL
t_ZH
t_LZ
Std.
0.66 2.31 0.04 1.25 0.43 2.35 1.84
t_HZ
t_ZLS t_ZHS Units
4.59 4.07 ns
–1
0.56 1.96 0.04 1.06 0.36 2.00 1.56
3.90 3.46 ns
–2
0.49 1.72 0.03 0.93 0.32 1.75 1.37
3.42 3.04 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
2-210
Revision 4