M1AFS600-PQ208 Datasheet, PDF (137/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Table 2-49 • Analog Channel Specifications (continued)
Commercial Temperature Range Conditions, T_J = 85°C (unless noted otherwise),
Typical: VCC33A = 3.3 V, VCC = 1.5 V
Parameter
Description
Condition
Min. Typ.
Max.
Units
Temperature Monitor Using Analog Pad AT
External
Resolution
Temperature
Monitor
(external diode
2N3904,
T_J = 25°C)⁴
Systematic Offset⁵
8-bit ADC
10-bit ADC
12-bit ADC
AFS090 uncalibrated⁷
AFS090, AFS250, calibrated⁷
4
°C
1
°C
0.25
°C
5
°C
0
°C
AFS250, AFS600, AFS1500,
uncalibrated⁷
AFS600, AFS1500, calibrated⁷
11
°C
0
°C
Accuracy
±3
±5
°C
External Sensor Source High level, TMSTBx = 0
10
µA
Current
Low level, TMSTBx = 1
100
µA
Max Capacitance on AT
pad
1.3
nF
Internal
Resolution
8-bit ADC
4
°C
Temperature
Monitor
10-bit ADC
1
°C
12-bit ADC
0.25
°C
Systematic Offset⁵
AFS090 uncalibrated⁷
5
°C
AFS090, AFS250, calibrated⁷
0
°C
AFS250, AFS600, AFS1500
uncalibrated⁷
AFS600, AFS1500 calibrated⁷
11
°C
0
°C
Accuracy
±3
±5
°C
t_TMSHI
t_TMSLO
t_TMSSET
Notes:
Strobe High time
Strobe Low time
Settling time
10
105
µs
5
µs
5
µs
1. VRSM is the maximum voltage drop across the current sense resistor.
2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no
reliability concern on digital inputs as long as VIND does not exceed these limits.
3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.
4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance
allowed across the AT pins is 500 pF.
5. The temperature offset is a fixed positive value.
6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on
voltage on the pad.
7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer
to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s
Guide.
Revision 4
2- 121