M1AFS600-PQ208 Datasheet, PDF (240/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Output DDR
Data_F
(from core)
A
FF1
B
CLK
CLKBUF
C
Data_R
(from core)
CLR
INBUF
D
FF2
B
C
Out
0
E
OUTBUF
1
DDR_OUT
Figure 2-144 • Output DDR Timing Model
Table 2-181 • Parameter Definitions
Parameter Name
Parameter Definition
t_DDROCLKQ
t_DDROCLR2Q
t_DDROREMCLR
t_DDRORECCLR
t_DDROSUD1
t_DDROSUD2
t_DDROHD1
t_DDROHD2
Clock-to-Out
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
Measuring Nodes (From, To)
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
2-224
Revision 4