M1AFS600-PQ208 Datasheet, PDF (51/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Real-Time Counter (part of AB macro)
The RTC is a 40-bit loadable counter and used as the primary timekeeping element (Figure 2-29). The
clock source, RTCCLK, must come from the CLKOUT signal of the crystal oscillator. The RTC can be
configured to reset itself when a count value reaches the match value set in the Match Register.
The RTC is part of the Analog Block (AB) macro. The RTC is configured by the analog configuration
MUX (ACM). Each address contains one byte of data. The circuitry in the RTC is powered by VCC33A,
so the RTC can be used in standby mode when the 1.5 V supply is not present.
Real-Time Counter
Control Status
xt_mode[1:0]
RTCXTLMODE[1:0]
xtal_en
RTCXTLSEL
ACM
Registers
1.5 V to
3.3 V
Level
Shifter
MatchBits Reg
Match Reg
Counter
Read-Hold Reg
Counter Reg
RTCMATCH
RTCPSMMATCH
RTCCLK
Crystal Prescaler
F_RTCCLK Divide by 128
40-Bit Counter
Figure 2-29 • RTC Block Diagram
Table 2-14 • RTC Signal Description
Signal Name
Width Direction
Function
RTCCLK
1
In Must come from CLKOUT of XTLOSC.
RTCXTLMODE[1:0] 2
Out Controlled by xt_mode in CTRL_STAT. Signal must connect to
the RTC_MODE signal in XTLOSC, as shown in Figure 2-27.
RTCXTLSEL
1
Out Controlled by xtal_en from CTRL_STAT register. Signal must
connect to RTC_MODE signal in XTLOSC in Figure 2-27.
RTCMATCH
1
Out Match signal for FPGA
0 – Counter value does not equal the Match Register value.
1 – Counter value equals the Match Register value.
RTCPSMMATCH
1
Out Same signal as RTCMATCH. Signal must connect to
RTCPSMMATCH in VRPSM, as shown in Figure 2-27.
The 40-bit counter can be preloaded with an initial value as a starting point by the Counter Register. The
count from the 40-bit counter can be read through the same set of address space. The count comes from
a Read-Hold Register to avoid data changing during read.
When the counter value equals the Match Register value, all Match Bits Register values will be
0xFFFFFFFFFF. The RTCMATCH and RTCPSMMATCH signals will assert. The 40-bit counter can be
configured to automatically reset to 0x0000000000 when the counter value equals the Match Register
value. The automatic reset does not apply if the Match Register value is 0x0000000000.
The RTCCLK has a prescaler to divide the clock by 128 before it is used for the 40-bit counter. Below is
an example of how to calculate the OFF time.
Revision 4
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