M1AFS600-PQ208 Datasheet, PDF (221/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-147 • Minimum and Maximum DC Input and Output Levels
2.5 V
GTL+
VIL
VIH
VOL VOH IOL IOH IOSL IOSH IIL¹ IIH²
Drive
Strength
Min.
V
Max.
V
Min.
V
Max. Max. Min.
Max. Max.
V
V
V
mA mA mA³ mA³ µA⁴ µA⁴
33 mA
–0.3 VREF – 0.1 VREF + 0.1 3.6 0.6
–
33 33 124 169 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
VTT
GTL+ ₂₅
Test Point
10 pF
Figure 2-127 • AC Loading
Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V)
VREF – 0.1
VREF + 0.1
1.0
1.0
1.5
Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.
C_LOAD (pF)
10
Timing Characteristics
Table 2-149 • 2.5 V GTL+
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.0 V
Speed
Grade t_DOUT t_DP
t_DIN
t_PY
t_EOUT
t_ZL
t_ZH
t_LZ
Std.
0.66 2.21 0.04 1.51 0.43 2.25 2.10
t_HZ
t_ZLS t_ZHS Units
4.48 4.34 ns
–1
0.56 1.88 0.04 1.29 0.36 1.91 1.79
3.81 3.69 ns
–2
0.49 1.65 0.03 1.13 0.32 1.68 1.57
3.35 4.34 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Revision 4
2- 205