M1AFS600-PQ208 Datasheet, PDF (75/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte order for read and write operations.
WD
RCLK
WCLK
RBLK
REN
ESTOP
WBLK
WEN
FSTOP
Reset
FREN
FWEN
CNT 12
E
=
AFVAL
CNT 12
E
SUB 12 ^AEVAL
=
WD[17:0]
RD[17:0]
RD
RCLK
WCLK
RADD[J:0]
WADD[J:0]
RAM
REN
WEN
FULL
AFULL
AEMPTY
EMPTY
Figure 2-47 • Fusion RAM Block with Embedded FIFO Controller
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