M1AFS600-PQ208 Datasheet, PDF (71/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Table 2-25 • Flash Memory Block Timing (continued)
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
t_SUPGLOSSPRO
t_HDPGLOSSPRO
t_SUPGSTAT
t_HDPGSTAT
t_SUOVERWRPG
t_HDOVERWRPG
t_{SULOCKREQUEST}
t_{HDLOCKREQUEST}
t_RECARNVM
t_REMARNVM
t_MPWARNVM
t_MPWCLKNVM
t_FMAXCLKNVM
Description
Page Loss Protect Setup Time for the Control Logic
Page Loss Protect Hold Time for the Control Logic
Page Status Setup Time for the Control Logic
Page Status Hold Time for the Control Logic
Over Write Page Setup Time for the Control Logic
Over Write Page Hold Time for the Control Logic
Lock Request Setup Time for the Control Logic
Lock Request Hold Time for the Control Logic
Reset Recovery Time
Reset Removal Time
Asynchronous Reset Minimum Pulse Width for the
Control Logic
Clock Minimum Pulse Width for the Control Logic
Maximum Frequency for Clock for the Control Logic – for
AFS1500/AFS600
Maximum Frequency for Clock for the Control Logic – for
AFS250/AFS090
–2
1.69
0.00
2.49
0.00
1.88
0.00
0.87
0.00
0.94
0.00
10.00
4.00
80.00
100.00
–1
1.93
0.00
2.83
0.00
2.14
0.00
0.99
0.00
1.07
0.00
12.50
5.00
80.00
80.00
Std.
2.27
0.00
3.33
0.00
2.52
0.00
1.16
0.00
1.25
0.00
12.50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.00 ns
80.00 MHz
80.00 MHz
Revision 4
2- 55