M1AFS600-PQ208 Datasheet, PDF (158/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Double Data Rate (DDR) Support
Fusion Pro I/Os support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every
transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity
requirements, making it very efficient for implementing very high-speed systems.
DDR interfaces can be implemented using HSTL, SSTL, LVDS, and LVPECL I/O standards. In addition,
high-speed DDR interfaces can be implemented using LVDS I/O.
Input Support for DDR
The basic structure to support a DDR input is shown in Figure 2-101. Three input registers are used to
capture incoming data, which is presented to the core on each rising edge of the I/O register clock.
Each I/O tile on Fusion devices supports DDR inputs.
Output Support for DDR
The basic DDR output structure is shown in Figure 2-102 on page 2-143. New data is presented to the
output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The
combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the
edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account
in the DDR macro.
Refer to the application note Using DDR for Fusion Devices for more information.
A
Data
INBUF
Input DDR
FF1
D _{Out_QF}
(to core)
B
CLK
CLKBUF
E _{Out_QR}
(to core)
FF2
CLR
C
INBUF
DDR_IN
Figure 2-101 • DDR Input Register Support in Fusion Devices
2-142
Revision 4