M1AFS600-PQ208 Datasheet, PDF (238/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
DDR Module Specifications
Input DDR Module
A
Data
INBUF
Input DDR
FF1
D _{Out_QF}
(to core)
B
CLK
CLKBUF
E _{Out_QR}
(to core)
FF2
CLR
C
INBUF
DDR_IN
Figure 2-142 • Input DDR Timing Model
Table 2-179 • Parameter Definitions
Parameter Name
Parameter Definition
t_DDRICLKQ1
t_DDRICLKQ2
t_DDRISUD
t_DDRIHD
t_DDRICLR2Q1
t_DDRICLR2Q2
t_DDRIREMCLR
t_DDRIRECCLR
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR Input
Data Hold Time of DDR Input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
Measuring Nodes (from, to)
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
2-222
Revision 4