M1AFS600-PQ208 Datasheet, PDF (164/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Temporary overshoots are allowed according to Table 3-4 on page 3-4.
Solution 1
Off-Chip
5.5 V
Fusion I/O Input
On-Chip
3.3 V
Rext1
Rext2
Requires two board resistors,
LVCMOS 3.3 V I/Os
Figure 2-103 • Solution 1
Solution 2
The board-level design must ensure that the reflected waveform at the pad does not exceed limits
provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used
for clamping, and the voltage must be limited by the external resistors and Zener, as shown in Figure 2-
104. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 2
Fusion I/O Input
Off-Chip On-Chip
5.5 V
3.3 V
Rext1
Zener
3.3 V
Figure 2-104 • Solution 2
Requires one board resistor, one
Zener 3.3 V diode, LVCMOS 3.3 V I/Os
2-148
Revision 4