M1AFS600-PQ208 Datasheet, PDF (320/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Datasheet Information
Revision
Revision 2
(continued)
July 2010
Changes
The "Examples" for calibrating accuracy for ADC channels were revised and
corrected to make them consistent with terminology in the associated tables (SARs
36791, 36773).
A note was added to Table 2-56 • Analog Quad ACM Byte Assignment and the
introductory text for Table 2-66 • Internal Temperature Monitor Control Truth Table,
stating that for the internal temperature monitor to function, Bit 0 of Byte 2 for all 10
Quads must be set (SAR 34418).
t_DOUT was corrected to t_DIN in Figure 2-116 • Input Buffer Timing Model and Delays
(example) (SAR 37115).
The formulas in the table notes for Table 2-97 • I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 34751).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34877).
The following notes were removed from Table 2-168 • Minimum and Maximum DC
Input and Output Levels (SAR 34808):
±5%
Differential input voltage = ±350 mV
An incomplete, duplicate sentence was removed from the end of the "GNDAQ
Ground (analog quiet)" pin description (SAR 30185).
Information about configuration of unused I/Os was added to the "User Pins" section
(SAR 32642).
The following information was added to the pin description for "XTAL1 Crystal
Oscillator Circuit Input" and "XTAL2 Crystal Oscillator Circuit Input" (SAR 24119).
The input resistance to ground value in Table 3-3 • Input Resistance of Analog Pads
for Analog Input (direct input to ADC), was corrected from 1 M (typical) to 2 k
(typical) (SAR 34371).
The Storage Temperature column in Table 3-5 • FPGA Programming, Storage, and
Operating Limits stated Min. T_J twice for commercial and industrial product grades
and has been corrected to Min. T_J and Max. T_J (SAR 29416).
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Dynamic Contribution—PCLOCK" section, was corrected to the
"Spine Architecture" section of the Global Resources chapter in the Fusion
FPGA Fabric User's Guide (SAR 34741).
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 36612).
The versioning system for datasheets has been changed. Datasheets are assigned
a revision number that increments each time the datasheet is revised. The "Fusion
Device Status" table indicates the status for each device in the device family.
Page
2-127
2-132,
2-134
2-164
2-174
2-178
2-212
2-226
2-228
2-230
3-4
3-5
3-24
4-1
N/A
5-4
Revision 4