M1AFS600-PQ208 Datasheet, PDF (228/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Differential I/O Characteristics
Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer
software when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires
that one data bit be carried through two signal lines, so two pins are needed. It also requires external
resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-134.
The building blocks of the LVDS transmitter–receiver are one transmitter macro, one receiver macro,
three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three
driver resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
OUTBUF_LVDS ^FPGA
Bourns Part Number: CAT16-LV4F12
P
165 
ZO = 50 
P
140 
100 
N
165 
ZO = 50 
N
FPGA
+
–
INBUF_LVDS
Figure 2-134 • LVDS Circuit Diagram and Board-Level Implementation
Table 2-168 • Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Typ.
Max.
Units
VCCI
Supply Voltage
2.375
2.5
2.625
V
VOL
Output Low Voltage
0.9
1.075
1.25
V
VOH
IOL ¹
IOH ¹
Input High Voltage
Output Low Voltage
Output High Voltage
1.25
1.425
1.6
V
0.65
0.91
1.16
mA
0.65
0.91
1.16
mA
VI
Input Voltage
0
IIL ^2,3
Input Low Voltage
IIH ^2,4
Input High Voltage
2.925
V
10
A
10
A
VODIFF
Differential Output Voltage
250
350
450
mV
VOCM
Output Common Mode Voltage
1.125
1.25
1.375
V
VICM
Input Common Mode Voltage
0.05
1.25
2.35
V
VIDIFF
Input Differential Voltage
100
350
mV
Notes:
1. IOL/IOH defined by VODIFF/(Resistor Network)
2. Currents are measured at 85°C junction temperature.
3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
2-212
Revision 4