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| M1AFS600-PQ208 Datasheet, PDF (274/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs | |||
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DC and Power Characteristics
Methodology
Total Power ConsumptionâPTOTAL
Operating Mode, Standby Mode, and Sleep Mode
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power ConsumptionâPSTAT
Operating Mode
PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) +
(NOUTPUTS * PDC8) + (NPLLS * PDC9)
NNVM-BLOCKS is the number of NVM blocks available in the device.
NQUADS is the number of Analog Quads used in the design.
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
NPLLS is the number of PLLs available in the device.
Standby Mode
PSTAT = PDC2
Sleep Mode
PSTAT = PDC3
Total Dynamic Power ConsumptionâPDYN
Operating Mode
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+
PXTL-OSC + PRC-OSC + PAB
Standby Mode
PDYN = PXTL-OSC
Sleep Mode
PDYN = 0 W
Global Clock Dynamic ContributionâPCLOCK
Operating Mode
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user designâguidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the Fusion and Extended
Temperature Fusion FPGA Fabric User's Guide.
NROW is the number of VersaTile rows used in the designâguidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the Fusion and Extended Temperature
Fusion FPGA Fabric User's Guide.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
Standby Mode and Sleep Mode
PCLOCK = 0 W
Sequential Cells Dynamic ContributionâPS-CELL
Operating Mode
3-24
Revision 4
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