M1AFS600-PQ208 Datasheet, PDF (152/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
CCC
Bank 0
CCC
Bank 1
CCC
Up to five VREF
minibanks within
an I/O bank
VREF signal scope is
between 8 and 18 I/Os.
Common VREF
signal for all I/Os
in VREF minibanks
I/O Pad
If needed, the VREF for a given
minibank can be provided by
any I/O within the minibank.
Figure 2-99 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)
Table 2-67 • I/O Standards Supported by Bank Type
I/O Bank
Single-Ended I/O Standards
Differential I/O
Standards
Voltage-Referenced
Hot-
Swap
Standard I/O LVTTL/LVCMOS 3.3 V, LVCMOS –
–
Yes
2.5 V / 1.8 V / 1.5 V, LVCMOS
2.5/5.0 V
Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL
and –
–
2.5 V / 1.8 V / 1.5 V, LVCMOS LVDS
2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-
X
Pro I/O
LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL
2.5 V / 1.8 V / 1.5 V, LVCMOS LVDS
2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-
X
and GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, Yes
HSTL Class I and II, SSTL2 Class I
and II, SSTL3 Class I and II
2-136
Revision 4